Diagnostics for Serial Communication Busses

ABSTRACT

The serial communication bus includes a first module coupled to a second module via a serial cable. Each of the first and second modules comprise one or more of: a power interface, a controller, memory, a first interface, and a second interface. The power interface is configured to receive operating power for the respective module from an external power source. The controller is configured to obtain digital diagnostic data representative of operational characteristics of at least the respective module. The memory is configured to store the digital diagnostic data. The first interface is configured to allow an external host to read the digital diagnostic data from the memory. The second interface, which is distinct and separate from the first interface, is configured to serially communicate data to the second module via the serial cable.

TECHNICAL FIELD

The disclosed embodiments relate generally to diagnostics for serial communication busses comprising a powered module coupled to a serial cable.

BACKGROUND

Hosts, such as storage devices (e.g., hard disk drives and optical drives) and storage device controllers, can communicate with each other via cables. Often, these cables are serial cables which transfer a single bit per clock cycle. Unfortunately, these serial cables do not include mechanisms that can monitor and/or store diagnostic data about the signals sent to and received from the hosts and/or the cables. Thus, the cause of a communication failure or degradation is difficult to determine, i.e. whether the host (or hosts) is failing or whether the serial cable is failing. For example, in a degrading system, a serial cable that is failing may produce the same symptoms (e.g., a degraded signal) as a host that is failing. Therefore, it would be highly desirable to provide a system and method for diagnosing operation or failure of a serial communication bus or link.

SUMMARY

Some embodiments provide a serial communication bus that includes a first module coupled to a second module via a serial cable. Each of these modules can be powered, i.e., receive power. As such, these types of serial communication busses are referred to as powered serial communication busses. The power is generally used to power active circuitry in the first and/or second modules. In some embodiments, each of the first and second modules comprises one or more of: a power interface, a controller, memory, a first interface, and a second interface. The power interface is configured to receive operating power for the respective module from an external power source. The controller is configured to obtain digital diagnostic data representative of operational characteristics of at least the respective module. The memory is configured to store the digital diagnostic data. The first interface is configured to allow an external host to read the digital diagnostic data from the memory. The second interface, which is distinct and separate from the first interface, is configured to serially communicate data to the second module via the serial cable.

In some embodiments, each of the first and second modules also includes a voltage controller and a voltage amplitude sensor. The voltage controller is configured to encode digital diagnostic data onto a serial data signal by adjusting voltage levels of the serial data signal sent to a host. The voltage amplitude sensor is configured to decode digital diagnostic data encoded onto a serial data signal by determining voltage levels of the serial data signal sent from a host.

Some embodiments provide a serial communication bus which includes a serial communications module. In some embodiments, the serial communications module includes a power interface, a controller, a first interface, and a second interface. The power interface is configured to receive operating power for the module from an external power source. The controller is configured to obtain digital diagnostic data representative of operational characteristics of the module, memory configured to store the digital diagnostic data. The first interface is configured to allow an external host to read the digital diagnostic data from the memory. The second interface is configured to serially communicate data to a second module via a serial cable coupled to the second interface circuit.

Some embodiments provide a method, an apparatus, and a computer-readable storage medium for transmitting encoded digital diagnostic data from a powered module to a requestor. In these embodiments, a request for digital diagnostic data for at least the serial cable and the powered module is received from a requestor. The digital diagnostic data is retrieved from memory of the powered module. The digital diagnostic data is then encoded onto a serial data signal while preserving the original data in the serial data signal. The serial data signal is then transmitted to the requestor.

Some embodiments provide a method, an apparatus and a computer-readable storage medium for decoding encoded digital diagnostic data. In these embodiments, a serial data signal which includes encoded digital diagnostic data is received from a sender. The digital diagnostic data is then obtained from the serial data signal. The digital diagnostic data is then stored to memory in a module of a serial cable.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an exemplary serial communication bus in accordance with some embodiments.

FIG. 2 is a block diagram illustrating an exemplary powered module for a serial cable in accordance with some embodiments.

FIG. 3 illustrates an exemplary memory map of a memory for a powered module in accordance with some embodiments.

FIG. 4A illustrates an exemplary voltage plot for a serial data signal in accordance with some embodiments.

FIG. 4B illustrates another exemplary voltage plot for a serial data signal in accordance with some embodiments.

FIG. 4C illustrates another exemplary voltage plot for a serial data signal in accordance with some embodiments.

FIG. 4D illustrates another exemplary voltage plot for a serial data signal in accordance with some embodiments.

FIG. 5 is a flow diagram of a process for transmitting encoded digital diagnostic data to a host in accordance with some embodiments.

FIG. 6 is a flow diagram of a process for decoding encoded digital diagnostic data in accordance with some embodiments.

Like reference numerals refer to corresponding parts throughout the drawings.

DESCRIPTION OF EMBODIMENTS

FIG. 1 is a block diagram illustrating an exemplary serial communication bus 100 in accordance with some embodiments. The serial communication bus 100 includes a module 101 coupled to a module 102 through a serial cable 103. The module 101 can be coupled to one or more hosts 104, 105, either directly or through the serial cable 103, as shown and the module 102 can be coupled to a host 105. In some embodiments, one or more of the modules 101 and 102, and the serial cable 103 are manufactured as a single unit that can be used to couple the one or more hosts 104, 105 to each other. In some embodiments, one or more of the modules 101, 102, and the serial cable 103 are manufactured as separate units that can be assembled by an end user in specified configurations to couple the one or more hosts 104, 105 to each other. In some embodiments, the serial cable 103 and/or the modules 101, 102 can include connectors (not shown) which are compliant with a serial communication standard, such as the Serial Advanced Technology Attachment (SATA) standard or the Serial Attached Small Computer System Interface (SAS) standard. In these embodiments, the modules 101, 102 and the serial cable 103 can communicate with each other using a serial communications protocol defined by the serial communication standard.

Existing serial cables are passive and rely on the hosts to provide the power to drive signals through the serial cables. Thus, in some embodiments, the modules 101, 102 are powered modules that include active circuitry. The active circuitry can include one or more of: active electronic components (e.g., transistors, diodes, processors, analog-to-digital converters, etc.) and passive electronic components (e.g., resistors, capacitors, inductors, etc.). In these embodiments, the modules 101, 102 can be powered by power sources 106, 107, respectively. In some embodiments, the power sources 106, 107 are included in the hosts 104, 105, respectively. Thus, the above-mentioned embodiments can be used to provide a powered SATA and/or a powered SAS serial cable. Note that the modules 101, 102 are described in more detail with reference to FIGS. 2-6 below.

In some embodiments, the serial cable 103 includes one or more of an optical cable and an electrically-conductive cable. The optical cable can include one or more optical fibers. Similarly, the electrically-conductive cable can include one or more electrically-conductive cables and/or wires. A hybrid cable (not shown) can include both electrically-conductive cables and optical fibers.

FIG. 2 is a block diagram illustrating a powered module 200 for a serial cable (e.g., the serial cable 103 in FIG. 1) in accordance with some embodiments. The powered module 200 can be any one of the modules 101, 102 in FIG. 1. As illustrated in FIG. 2, the powered module 200 is coupled to a host 240. Note that the host 240 can be any one of the hosts 104, 105 illustrated in FIG. 1. The powered module 200 can also be coupled to optical fibers or electrical cables 220 which can transmit data encoded in optical signals from the powered module 200 to another powered module (e.g., the modules 101, 102 in FIG. 1) or to another host (e.g., the hosts 104, 105 in FIG. 1) via a first interface 260. In some embodiments, the optical fibers or electrical cable 220 are coupled to the second interface 262.

The powered module 200 includes one or more of: a host interface 202, a controller 204, a memory controller 206, a memory 208, a post-amplifier 212, sensors 210, a receiver 214, a driver 216, a transmitter 218, a power interface 250, a voltage amplitude sensor 230, a voltage controller 232, and a clock data recovery (CDR) circuit 234. Note that for an optoelectronic module, the post-amplifier 212, the receiver 214, the driver 216, and the transmitter 218 can be referred to as an optical interface (e.g., the second interface 262) for the optical fibers 220. Alternatively, for an electrical module, the receiver 214 and the transmitter 218 can be referred to as an electrical interface (e.g., the second interface 262) for the cables 220. Similarly, one or more of the host interface 202 and the power interface 250 can be referred to as the first interface 260.

In some embodiments, the memory 208 can include a magnetic or optical disk storage device, solid state storage devices such as Flash memory, or other non-volatile and/or volatile memory device or devices. In some embodiments, the memory 208 includes a non-volatile memory for storing programs and/or data and includes a volatile memory that can be used during the runtime of the stored programs.

In some embodiments, the host interface 202 allows the host 240 to communicate with the powered module 200. For example, the host interface 202 can allow the host 240 to access data stored in the memory 208. Similarly, the host interface 202 can allow the host 240 to send data and/or commands through and to receive data and/or commands from the optical fibers or electrical cables 220. In some embodiments, the host interface 202 allows the host 240 to read data from and/or to write data to the memory 208. In some embodiments, data can be read from and/or written to the memory 208. The data can include digital diagnostic data for the powered module 200 and/or the optical fibers or electrical cables 220. In some embodiments, the digital diagnostic data includes one or more of: one or more serial number, transfer speed of the serial cable, a voltage amplitude and/or a power level of a signal received from the serial cable, a voltage amplitude and/or a power level of a signal received from the host, an optical power level of an optical signal received from the serial cable, measures of signal quality (e.g., vertical and horizontal eye opening sizes for signals received from the serial cable), an expected signal loss based on the type of the serial cable, number of faults, power supply voltage for powered module, bias current level for an optical transceiver, a status of an equalizer for a receiver in the powered module (e.g., decision feedback equalizer coefficients and/or analog settings), a pre-emphasis and receiver equalization settings and thresholds, and the number of times the serial cable has been plugged in. In some embodiments, the data and/or commands received at the host 240 can be stored in the memory 244 within the host 240. In some embodiments, the host interface 202 is an electrical interface. In some embodiments, the host interface 202 communicates with the host 240 using one or more of: a Serial Advanced Technology Attachment (SATA) protocol, and a Serial Attached Small Computer System Interface (SAS) protocol.

In some embodiments, the controller 204 can perform a number of operations, including but not limited to, managing tasks within the powered module 200, controlling components within the powered module 200, monitoring operating characteristics of the powered module 200 and/or the optical fibers or electrical cables 220, and accessing data, such as digital diagnostic data representative of operational characteristics of the powered module 200 and/or the optical fibers or electrical cables 220.

In some embodiments, the controller 204 can receive commands issued by the host 240 through the host interface 202 instructing the controller 204 to retrieve data from the memory 208. In these embodiments, the controller 204 issues read commands to the memory controller 206, which in turn retrieves the requested data from specified locations within the memory 208 and returns the requested data to the controller 204. Alternatively, the memory controller 206 can be optional and the controller 204 issues read commands directly to the memory 208. The controller 204 then returns the requested data to the host 240 through the host interface 202. In some embodiments, the data includes digital diagnostic data for the powered module 200 and/or the optical fibers or electrical cables 220. In some embodiments, the host 240 can read data directly from the memory 208, bypassing the controller 204.

In some embodiments, the controller 204 can receive commands and/or data issued by the host 240 through the host interface 202 instructing the controller 204 to write the received data to the memory 208. In these embodiments, the controller 204 issues write commands including the received data to the memory controller 206, which in turn writes the requested digital diagnostic data to specified locations within the memory 208. Alternatively, the memory controller 206 can be optional and the controller 204 issues write commands including the received data directly to the memory 208. In some embodiments, the data includes digital diagnostic data for the powered module 200 and/or the optical fibers or electrical cables 220. In some embodiments, the host 240 can write the data directly to the memory 208, bypassing the controller 204.

In some embodiments, the controller 204 can receive commands from another powered module (not shown) coupled to the optical fibers or electrical cables 220 or from another host coupled to the optical fibers or electrical cables 220 (not shown) instructing the controller 204 to retrieve data from the memory 208.

When the optical fibers or electrical cables 220 include optical fibers, optical signals including the commands are sent through the optical fibers 220 to the receiver 214 which converts the optical signals into electrical signals. In some embodiments, the receiver 214 is a photodiode which can convert optical signals into electrical signals. These electrical signals can first be sent to the post-amplifier 212, which generates a fixed output signal, before being sent to the controller 204. Alternatively, the electrical signals can be sent to the controller 204 without first being processed by the post-amplifier 212. In some embodiments, if the optical signals include serialized commands, the serialized commands can first be deserialized to reconstruct the commands. The controller 204 then issues read commands to the memory controller 206, which in turn retrieves the requested data from specified locations within the memory 208 and returns the requested data to the controller 204. Alternatively, the controller 204 issues read commands directly to the memory 208 to retrieve the requested data from specified locations within the memory 208 and returns the requested data to the controller 204. The controller 204 can then send the data to the driver 216, which drives the transmitter 218. In some embodiments, the transmitter 218 is a laser transmitter and the driver 216 is a laser driver. Alternatively, the controller 204 can send the data to the transmitter 218 without using the driver 216. In either case, the transmitter 218 converts the electrical signals into optical signals which are then transmitted through the optical fibers 220 to the other powered module or to the other host. In some embodiments, the data can first be serialized before being transmitted through the optical fibers 220. In some embodiments, the data includes digital diagnostic data for the powered module 200 and/or the optical fibers 220.

When the optical fibers or electrical cables 220 include electrical cables, electrical signals including the commands are sent through the electrical cables 220 to the receiver 214. In some embodiments, if the electrical signals include serialized commands, the serialized commands can first be deserialized to reconstruct the commands. The controller 204 then issues read commands to the memory controller 206, which in turn retrieves the requested data from specified locations within the memory 208 and returns it to the controller 204. Alternatively, the controller 204 issues read commands directly to the memory 208 to retrieve the requested data from specified locations within the memory 208 and returns the requested data to the controller 204. The controller 204 can then send the data to the transmitter 218. The transmitter 218 then transmits the data through the electrical cables 220 to the other powered module or to the other host. In some embodiments, the data can first be serialized before being transmitted through the electrical cables 220. In some embodiments, the data includes digital diagnostic data for the powered module 200 and/or the electrical cables 220.

In some embodiments, the controller 204 can receive commands and/or data from another powered module (not shown) coupled to the optical fibers or electrical cables 220 or from another host coupled to the optical fibers or electrical cables 220 (not shown) instructing the controller 204 to store data to the memory 208.

When the optical fibers or electrical cables 220 include optical fibers, optical signals including the commands and/or the data are sent through the optical fibers 220 to the receiver 214 which converts the optical signals into electrical signals. These electrical signals can first be sent to the post-amplifier 212 before being sent to the controller 204. Alternatively, the electrical signals can be sent directly to the controller 204. In some embodiments, if the optical signals include serialized commands, the serialized commands can first be deserialized to reconstruct the commands. The controller 204 then issues write commands including the data to the memory controller 206, which in turn writes the data to specified locations within the memory 208. Alternatively, the controller 204 issues write commands including the data directly to the memory 208 to write the data to specified locations within the memory 208. In some embodiments, the data includes digital diagnostic data for the powered module 200 and/or the optical fibers 220.

When the optical fibers or electrical cables 220 include electrical cables, electrical signals including the commands and/or the data are sent through the electrical cables 220 to the receiver 214. These electrical signals can be sent to the controller 204. In some embodiments, if the electrical signals include serialized commands, the serialized commands can first be deserialized to reconstruct the commands. The controller 204 then issues write commands including the data to the memory controller 206, which in turn writes the requested data to specified locations within the memory 208. Alternatively, the controller 204 issues write commands including the data directly to the memory 208 to write the data to specified locations within the memory 208. In some embodiments, the data includes digital diagnostic data for the powered module 200 and/or the electrical cables 220.

In some embodiments, the host 240 can send data and/or commands to another host (not shown) or another powered module (not shown) through the optical fibers or electrical cables 220.

When the optical fibers or electrical cables 220 include optical fibers, the host 240 can send the data and/or the commands to the host interface 202. The host interface 202 can then send the data and/or the commands to the driver 216, which drives the transmitter 218. The transmitter 218 then converts the electrical signals into optical signals which are sent through the optical fibers 220 to the other host or to the other powered module. Alternatively, the host interface 202 can send the data and/or commands to the controller 204, which can send the data and/or commands to the driver 216 or the transmitter 218. Alternatively, the host interface 202 can send the data and/or the commands to the driver 216 or the transmitter 218, bypassing the controller 204. In some embodiments, the data and/or commands are first serialized before being transmitted through the optical fibers 220.

When the optical fibers or electrical cables 220 include electrical cables, the host 240 can send the data and/or the commands to the host interface 202. The host interface 202 can send the data and/or the commands to the transmitter 218. The transmitter 218 transmits the data and/or commands through the electrical cables 220 to the other host or to the other powered module. Alternatively, the host interface 202 can send the data and/or commands to the controller 204, which can send the data and/or commands to the transmitter 218. Alternatively, the host interface 202 can send the data and/or the commands to the transmitter 218, bypassing the controller 204. In some embodiments, the data and/or commands are first serialized before being transmitted through the electrical cables 220.

In some embodiments, the host 240 can receive data and/or commands from another host (not shown) or another powered module (not shown) through the optical fibers or electrical cables 220.

When the optical fibers or electrical cables 220 include optical fibers, optical fibers, the receiver 214 can receive data and/or commands through the optical fibers 220 from the other host or the other powered module. The receiver 214 converts the optical signals into electrical signals. In some embodiments, if the data and/or the commands are serialized, they are first deserialized. The receiver 214 can send the data and/or the commands to the post-amplifier 212, which sends the data to the controller 204. The controller 204 can then send the data and/or the commands to the host interface 202. Alternatively, the receiver 214 can send the data and/or the commands to the controller 204, bypassing the post-amplifier 212. Alternatively, the receiver 214 or the post-amplifier 212 can send the data and/or the command to the host interface 202, bypassing the controller 204. The host interface 202 then sends the data and/or the commands to the host 240.

When the optical fibers or electrical cables 220 include electrical cables, the receiver 214 can receive data and/or commands through the electrical cables 220 from the other host or the other powered module. In some embodiments, if the data and/or the commands are serialized, they are first deserialized. The receiver 214 can send the data and/or the commands to the controller 204. The controller 204 can then send the data and/or the commands to the host interface 202. Alternatively, the receiver 214 can send the data and/or the command to the host interface 202, bypassing the controller 204. The host interface 202 then sends the data and/or the commands to the host 240.

In some embodiments, the host 240 receives additional data (e.g., digital diagnostic data) encoded in a serial data signal. For example, the serial data signal can include data and/or commands used by two hosts to communicate with each other, as described above. In some embodiments, the additional data can be encoded onto a serial data signal while preserving the original data in serial data signal. For example, for a given data bit, the data bit can include the original data as well as the additional data. These embodiments are beneficial in systems where the standard requires a specified protocol to be used when transmitting data to and from hosts.

FIGS. 4A-4D illustrate exemplary technique for encoding additional data (e.g., digital diagnostic data) onto serial data signals. In FIGS. 4A-4D, an exemplary serial data signal 402 can have a high voltage level (V_(H)) and a low voltage level (V_(L)). The high voltage level can correspond to a logical one and the low voltage level can correspond to a logical zero. In FIGS. 4A-4D, the serial data signal 402 includes the following data: 0101010.

In some embodiments, an encoded serial data signal can be produced from the serial data signal 402 by modifying the high voltage level and the low voltage level of the serial data signal 402. The encoded serial data signal can include additional data, such as digital diagnostic data. For example, the voltage controller 232 in FIG. 2 can be configured to adjust the amplitude of the voltage level for the serial data signal 402 to encode additional data onto the serial data signal 402. In some embodiments, the voltage level for the serial data signal is adjusted based on the additional data to be encoded onto the serial data signal 4502 and a voltage map which maps data values to voltage levels. In doing so, the encoded serial data signal can be produced. When an encoded serial data signal is received, the encoded serial data signal can be decoded. For example, the voltage amplitude sensor 230 in FIG. 2 can be configured to determine the amplitude of the voltage level for the encoded serial data signal. In some embodiments, a voltage map can be used to map the determined amplitude of the voltage level to one or more data values. In doing so, the additional data encoded on the encoded serial data signal can be extracted.

In some embodiments, the high voltage level and the low voltage levels of the serial data signal 402 are adjusted by a specified voltage (e.g., a specified percentage increase or decrease) to produce encoded serial data signals that include additional data. In some embodiments, the new high voltage level and the new low voltage level can be selected to be within the noise margins for the high voltage level and the low voltage level of a receiver which receives the encoded serial data signal. In other words, the receiver can detect a high voltage level (e.g., the original data) when the encoded serial data signal is either at the original high voltage level or at the new high voltage level (or anywhere in between). Similarly, the receiver can detect a low voltage level (e.g., the original data) when the encoded serial data signal is either at the original low voltage level or at the new low voltage level (or anywhere in between). Thus, both the original data in the serial data signal 402 and the additional data can be encoded onto the serial data signal 402. Using this encoding technique, the original high voltage level and the original low voltage level can be used to represent a logical zero for the additional data, whereas the new high voltage level and the new low voltage level can be used to represent a logical one for the additional data. Alternatively, the original high voltage level and the original low voltage level can be used to represent a logical one for the original data, whereas the new high voltage level and the new low voltage level can be used to a represent logical zero for the additional data. These embodiments are illustrated in FIGS. 4A-4D.

In FIG. 4A, the high voltage level and the low voltage level of the serial data signal 402 have been increased by a specified voltage (e.g., a specified percentage increase) at specified bits of the serial data signal 402 to produce an encoded serial data signal 404 with the following additional data: 1101101. As illustrated in FIG. 4A, the new voltage levels V_(H1) and V_(L1) are used to encode logical ones for the encoded serial data signal 404. When the encoded serial data signal 404 is at V_(H1) (e.g., when the serial data signal 402 is high) or at V_(L1) (e.g., when the serial data signal 402 is low), a logical one is detected for the additional data, and when the encoded serial data signal 404 is at V_(H) or V_(L), a logical zero is detected for the additional data. Thus, in addition to the original serial data signal 402, the additional data (e.g., 1101101) encoded in the encoded serial data signal 404 can be extracted. Note that the role of V_(H), V_(H1), V_(L), and V_(L) can be mapped in any combination. For example, V_(H) can correspond to a logical one for the additional data, V_(H1) can correspond to a logical zero for the additional data, V_(L) can correspond to a logical zero for the additional data, and V_(L) can correspond to a logical one for the additional data. In some embodiments, a voltage encoding map can be used to decode data encoded using this technique.

In FIG. 4B, the high voltage level and the low voltage level of the serial data signal 402 have been decreased by a specified voltage (e.g., a specified percentage decrease) at specified bits of the serial data signal 402 to produce an encoded serial data signal 406 with the same additional data as described in FIG. 4A (e.g., 1101101). As illustrated in FIG. 4B, the new voltage levels V_(H2) and V_(L2) are used to encode logical ones for the encoded serial data signal 406. When the encoded serial data signal 406 is at V_(H2) (e.g., when the serial data signal 402 is high) or at V_(L2) (e.g, when the serial data signal 402 is low), a logical one is detected, and when the encoded serial data signal 406 is at V_(H) or V_(L), a logical zero is detected. Thus, in addition to the original serial data signal 402, the additional data (e.g., 1101101) encoded in the encoded serial data signal 406 can be extracted. As noted above, the roles of V_(H), V_(H2), V_(L), and V_(L2) can be mapped in any combination. Again, a voltage encoding map can be used to decode data encoded using this technique.

In FIG. 4C, the high voltage level and the low voltage level of the serial data signal 402 have been increased and decreased, respectively, by a specified voltage (e.g., a specified percentage increase and decrease, respectively) at specified bits of the serial data signal 402 to produce an encoded serial data signal 408 with the same additional data as described in FIG. 4A (e.g., 1101101). As illustrated in FIG. 4C, the new voltage levels V_(H3) and V_(L3) are used to encode logical ones for the encoded serial data signal 408. When the encoded serial data signal 408 is at V_(H3) (e.g., when the serial data signal 402 is high) or at V_(L3) (e.g., when the serial data signal 402 is low), a logical one is detected, and when the encoded serial data signal 408 is at V_(H) or V_(L), a logical zero is detected. Thus, in addition to the original serial data signal 402, the additional data (e.g., 1101101) encoded in the encoded serial data signal 408 can be extracted. As noted above, the roles of V_(H), V_(H3), V_(L), and V_(L3) can be mapped in any combination. Again, a voltage encoding map can be used to decode data encoded using this technique.

Note that any combination of increased or decreased voltage levels can be used. Furthermore, a plurality of voltage levels can be used. For example, in FIG. 4D, the additional data can be encoded onto a plurality of voltage levels V_(H4), V_(H5), V_(H6), V_(L4), V_(L5), and V_(L6). A exemplary voltage mapping for the additional data may be: V_(H)=0, V_(H4)=1, V_(H5)=2, V_(H6)=3, V_(L)=0, V_(L4)=1, V_(L5)=2, and V_(L6)=3. Thus, the additional data encoded serial data signal 410 is: 2, 2, 1, 3, 3, 1, 3. Again, a voltage encoding map can be used to decode data encoded using this technique.

Other encoding techniques can be used, including, but not limited to, reencoding the original serial data signal and the additional data onto one or more adjusted voltage levels. For example, consider an encoding technique where the original high voltage level is 1.5V and the original low voltage level is 0V. The new high voltage level can then be set to 1.6V and the new low voltage level can be set to 0.1V. Since there are two data streams to be encoded (e.g., the original serial data stream and the additional diagnostics data stream) onto a single serial data stream, there are four possible combinations of logical values of the two data streams: (state 1) 0 for the original data and 0 for the additional data, (state 2) 0 for the original data and 1 for the additional data, (state 3) 1 for the original data and 0 for the additional data, (state 4) 1 for the original data and 1 for the additional data. The following exemplary voltage encoding can be used: the 0V level is associated with state 1, the 0.1V level is associated with state 2, the 1.5V level is associated with state 3, and the 1.6V level is associated with state 4. Note that any variations on the specified voltage levels, the combinations of logical values within a given state, and/or the mapping of those combinations to the specified voltage levels can be used. In order to use this type of reencoding, the transmitters and/or receivers (and/or associated circuitry such as the controllers) need to be configured to use the appropriate voltage encoding map to decode the encoded serial data signal to extract the original serial data and the additional data.

Returning to FIG. 2, when the optical fibers or electrical cables 220 include optical fibers, in some embodiments, the voltage amplitude sensor 230 receives electrical signals from the post-amplifier 212 or the receiver 214 (not shown in FIG. 2). In these embodiments, the electrical signal can be encoded using a technique as described above. In some embodiments, the amplitude of an optical signal received through the optical fibers 220 is adjusted so that electrical signals produced by the receiver 214 and/or the post-amplifier 212 include voltage levels that can be used to encode additional data onto the original serial data signal (e.g., as described above).

In some embodiments, when the optical fibers or electrical cables 220 include electrical cables, the voltage amplitude sensor 230 receives electrical signals from the receiver 214 (not shown in FIG. 2). In these embodiments, the electrical signal can be encoded using a technique as described above. In some embodiments, the amplitude of an electrical signal received through the electrical cables 220 is adjusted so that electrical signals produced by the receiver 214 include voltage levels that can be used to encode additional data onto the serial data signal (e.g., as described above).

In some embodiments, when the optical fibers or electrical cables 220 include optical fibers, the optical signals received through the optical fibers 220 include both the original serial data and the additional data in an uncombined form (e.g., the additional data signal is not encoded onto the original serial data signal). For example, the original serial data and the additional data can be transmitted on different optical carrier frequencies in parallel in the same optical fiber. Similarly, the original serial data and the additional data can be transmitted through parallel optical fibers. In these embodiments, the controller 204 can receive the separate signals from the receiver 214 or the post-amplifier 212 and process them according to specified rules and/or commands. For example, the controller 204 can send the original serial data to the host interface 202, which in turn transmits the original serial data to the host 240. Alternatively, the controller 204 can send the original serial data and the additional data to the voltage controller 232 so that the additional data can be encoded onto the original serial data prior to being sent to the host 240.

In some embodiments, when the optical fibers or electrical cables 220 include electrical signals, the electrical signal received through the electrical cables 220 includes both the original serial data and the additional data in an uncombined form (e.g., the additional data signal is not encoded onto the original serial data signal). For example, the original serial data and the additional data can be transmitted on parallel cables and/or wires. In these embodiments, the controller 204 can receive the separate signals from the receiver 214 and process them according to specified rules and/or commands. For example, the controller 204 can send the original serial data to the host interface 202, which in turn transmits the original serial data to the host 240. Alternatively, the controller 204 can send the original serial data and the additional data to the voltage controller 232 so that the additional data can be encoded onto the original serial data prior to being sent to the host 240.

In some embodiments, when the optical fibers or electrical cables 220 include optical fibers, the optical signals received through the optical fibers 220 includes both the original serial data and the additional data in encoded form (e.g., using the techniques described above or other techniques). In these embodiments, the receiver 214 or the post-amplifier 212 can decode the encoded signal to extract the original serial data and the additional data.

In some embodiments, when the optical fibers or electrical cables 220 include electrical cables, the electrical signals received through the electrical cables 220 includes both the original serial data and the additional data in encoded form (e.g., using the techniques described above or other techniques). In these embodiments, the receiver 214 can decode the encoded signal to extract the original serial data and the additional data.

In some embodiments, when the optical fibers or electrical cables 220 include optical fibers, the voltage controller 232 encodes additional data onto an original serial data signal which is to be converted into optical signals by the transmitter 218 for transmission through the optical fibers 220. For example, the encoding techniques described above can be used. In some embodiments, the amplitude of an optical signal generated by the transmitter 218 is adjusted so that electrical signals produced by a receiver and/or a post-amplifier include voltage levels that can be used to encode additional data onto the original serial data signal (e.g., as described above).

In some embodiments, when the optical fibers or electrical cables 220 include electrical cables, the voltage controller 232 encodes additional data onto a original serial data signal which is to be transmitted by the transmitter 218 through the electrical cables 220. For example, the encoding technique described above can be used. In some embodiments, the amplitude of an electrical signal generated by the transmitter 218 is adjusted so that electrical signals produced by a receiver include voltage levels that can be used to encode additional data onto the original serial data signal (e.g., as described above).

In some embodiments, when the optical fibers or electrical cables 220 include optical fibers, the optical signal transmitted through the optical fibers 220 includes both the original serial data and the additional data in an uncombined form (e.g., the additional data signal is not encoded onto the original serial data signal). For example, the original serial data and the additional data can be transmitted on different optical carrier frequencies in parallel in the same optical fiber. Similarly, the original serial data and the additional data can be transmitted through parallel optical fibers.

In some embodiments, when the optical fibers or electrical cables 220 include electrical cables, the electrical signals transmitted through the electrical cables 220 include both the original serial data and the additional data in an uncombined form (e.g., the additional data signal is not encoded onto the original serial data signal). For example, the original serial data and the additional data can be transmitted on parallel cables.

In some embodiments, when the optical fibers or electrical cables 220 include optical fibers, the optical signal transmitted through the optical fibers 220 includes both the original serial data and the additional data in encoded form (e.g., using the techniques described above or other techniques). In these embodiments, the driver 216 or the transmitter 218 can encode the original serial data and the additional data onto a single signal stream.

In some embodiments, when the optical fibers or electrical cables 220 include electrical cables, the electrical signals transmitted through the electrical cables 220 includes both the original serial data and the additional data in encoded form (e.g., using the techniques described above or other techniques). In these embodiments, the transmitter 218 can encode the original serial data and the additional data onto a single signal stream.

In some embodiments, the sensors 210 include one or more of voltage sensors, current sensors, temperature sensors, and accelerometers.

The CDR circuit 234 can be used to extract data from a data stream when an associated clock is not sent with the data stream. Note that CDR circuits are well known in the art.

In some embodiments, the power interface 250 can be coupled to the power source 242 in the host 240. In other embodiments, the power interface 250 can be coupled to a power source that is external to the host 240.

As mentioned above, the host 240 typically communicates with another host using a specified communication protocol defined in a specified standard (e.g., SAS or SATA). Although the host 240 can communicate with the powered module using the specified communication protocol, in some embodiments, the powered module 200 can use a different communication protocol when sending the data and/or commands through the optical fibers or electrical cables 220 to another powered module. In these embodiments, the powered module 200 performs the required translations between the different communication protocols. In other embodiments, the powered module 200 uses the same communication protocol as the host 240 when sending the data and/or commands to another host.

Note that the powered module 200 can include more or fewer components than illustrated in FIG. 2. Furthermore, the individual components can be combined with each other. For example, when the optical fibers or electrical cables 220 include optical fibers, the receiver 214 and the post-amplifier 212 can be combined into a single component, and the transmitter 218 and the driver 216 can be combined into a single component. Similarly, when the optical fibers or electrical cables 220 include electrical cables, the receiver 214 and the transmitter 218 can be combined into a single component.

FIG. 3 illustrates an exemplary memory map 300 of a memory for a powered module in accordance with some embodiments. In some embodiments, the memory map 300 can be a memory map for the memory 208 in FIG. 2. In some embodiments, the memory map 300 can be a memory map for the memory 244 in FIG. 2. An exemplary memory map is presented in Table 1.

In some embodiments the memory stores the following programs, modules and data structures, or a subset thereof: status flags 302, monitored values 304, control values 306, identifying information 308, control procedures 310, and monitoring procedures 312.

The status flags 302 may include comparisons of operating conditions with warning alarms. In some embodiments, the status flags 302 may include low and high level alarm flags.

The monitored values 304 may include values associated with an operating condition of the powered module. These values can also be referred to as digital diagnostic data. For example, the digital diagnostic data can include one or more of: one or more serial number, transfer speed of the serial cable, a voltage amplitude and/or a power level of a signal received from the serial cable, a voltage amplitude and/or a power level of a signal received from the host, an optical power level of an optical signal received from the serial cable, measures of signal quality (e.g., vertical and horizontal eye opening sizes for signals received from the serial cable), an expected signal loss based on the type of the serial cable, number of faults, power supply voltage for powered module, bias current level for an optical transceiver, a status of an equalizer for a receiver in the powered module (e.g., decision feedback equalizer coefficients and/or analog settings), a pre-emphasis and receiver equalization settings and thresholds, and the number of times the serial cable has been plugged in. Exemplary status flags and monitored values are presented in Table 2, and exemplary alarm and warning flags are presented in Table 3.

The control values 306 may include values associated with controlling the operation of the powered module, e.g., threshold values or the like. Exemplary configuration and/or control values are presented in Table 4.

The identifying information 308 may include information identifying the powered module, the cables, and/or the components within the powered module. The identifying information can include serial numbers or other types of identifiers. Note that the identifying information can also be included in the digital diagnostic data.

In some embodiments, the memory may include the control procedures 310 and the monitoring procedures 312 which can be executed by a controller and/or a processor within the powered module (e.g. the controller 204). The control procedures 310 may include programs used in the operation of the transmitter and the receiver. The monitoring procedures 312 may include programs used to monitor the status of components and to take measurements of operating conditions associated with the components (e.g., voltages, temperatures, optical power, etc.).

FIG. 5 is a flowchart representing a method 500 for transmitting encoded digital diagnostic data to a host, according to some embodiments. The method 500 may be governed by instructions that are stored in a computer readable storage medium (e.g., the memory 208) and that are executed by one or more processors (e.g., the controller 204). Each of the operations shown in FIG. 6 may correspond to instructions stored in a computer memory or computer readable storage medium. The computer readable storage medium may include a magnetic or optical disk storage device, solid state storage devices such as Flash memory, or other non-volatile memory device or devices. The computer readable instructions stored on the computer readable storage medium are in source code, assembly language code, object code, or other instruction format that is interpreted by one or more processors.

In some embodiments, prior to receiving a request for the digital diagnostic data, at least the serial cable and the powered module are monitored to obtain digital diagnostic data (502) and the obtained digital diagnostic data is stored into the memory of the powered module (504). In some embodiments, the monitoring is performed by one or more of the powered module and an external device (e.g., a host, a diagnostic test device, etc.). In some embodiments, the monitoring is performed periodically.

A powered module receives a request for digital diagnostic data for at least the serial cable and the powered module from a requestor (506). In some embodiments, the requestor includes one or more of a host system and another powered module.

After receiving the request for the digital diagnostic data, the powered module retrieves the digital diagnostic data from memory of the powered module (508). Next, the powered module encodes the digital diagnostic data onto a serial data signal while preserving the original data in the serial data signal (510). In some embodiments, the encoding includes: serializing the digital diagnostic data (520), determining a series of voltage levels for the serialized digital diagnostic data based on a voltage encoding map (522), and adjusting voltage levels for the serial data signal based on the determined series of voltage levels (524).

After encoding the digital diagnostic data onto the serial data signal, the powered module transmits the serial data signal to the requester (512).

FIG. 6 is a flowchart representing a method 600 for decoding encoded digital diagnostic data, according to some embodiments. The method 600 may be governed by instructions that are stored in a computer readable storage medium (e.g., the memory 208) and that are executed by one or more processors (e.g., the controller 204). Each of the operations shown in FIG. 7 may correspond to instructions stored in a computer memory or computer readable storage medium. The computer readable storage medium may include a magnetic or optical disk storage device, solid state storage devices such as Flash memory, or other non-volatile memory device or devices. The computer readable instructions stored on the computer readable storage medium are in source code, assembly language code, object code, or other instruction format that is interpreted by one or more processors.

The one or more processors receive a serial data signal which includes encoded digital diagnostic data from a sender (602). In some embodiments, the sender includes one of a powered module and a host system.

Next, the one or more processors obtain the digital diagnostic data from the serial data signal (604). In some embodiments, the obtaining includes: determining a series of voltage levels for the serial data signal (620), obtaining serialized digital diagnostic data from the determined series of voltage levels based on a voltage encoding map (622), and deserializing the serialized digital diagnostic data to obtain the digital diagnostic data (624).

After obtaining the digital diagnostic data, the one or more processors store the digital diagnostic data to memory (606). In some embodiments, the memory is one of a memory for a powered module and a memory for a host system.

The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.

TABLE 1 MEMORY MAP FOR CONTROLLER Name of Location Function Memory Location (Array 0) 00h-5Fh IEEE Data This memory block is used to store required GBIC data 60h Temperature MSB This byte contains the MSB of the 15-bit 2's complement temperature output from the temperature sensor. 61h Temperature LSB This byte contains the LSB of the 15-bit 2's complement temperature output from the temperature sensor. (LSB is 0 b). 62h-63h V_(cc) Value These bytes contain the MSB (62h) and the LSB (63h) of the measured V_(cc) (15-bit number, with a 0 b LSbit) 64h-65h B_(in) Value These bytes contain the MSB (64h) and the LSB (65h) of the measured B_(in) (15-bit number, with a 0 b LSbit) 66h-67h P_(in) Value These bytes contain the MSB (66h) and the LSB (67h) of the measured P_(in) (15-bit number, with a 0 b LSbit) 68h-69h R_(in) Value These bytes contain the MSB (68h) and the LSB (69h) of the measured R_(in) (15-bit number, with a 0 b LSbit) 6Ah-6Dh Reserved Reserved 6Eh IO States This byte shows the logical value of the I/O pins. 6Fh A/D Updated Allows the user to verify if an update from the A/D has occurred to the 5 values: temperature, V_(cc), B_(in), P_(in) and R_(in). The user writes the byte to 00h. Once a conversion is complete for a give value, its bit will change to ‘1’. 70h-73h Alarm Flags These bits reflect the state of the alarms as a conversion updates. High alarm bits are ‘1’ if converted value is greater than corresponding high limit. Low alarm bits are ‘1’ if converted value is less than corresponding low limit. Otherwise, bits are 0 b. 74h-77h Warning Flags These bits reflect the state of the warnings as a conversion updates. High warning bits are ‘1’ if converted value is greater than corresponding high limit. Low warning bits are ‘1’ if converted value is less than corresponding low limit. Otherwise, bits are 0 b. 78h-7Ah Reserved Reserved 7Bh-7Eh Password Entry Bytes The four bytes are used for password entry. PWE Byte 3 (7Bh) The entered password will determine the MSByte user's read/write privileges. PWE Byte 2 (7Ch) PWE Byte 1 (7Dh) PWE Byte 0 (7Eh) LSByte 7Fh Array Select Writing to this byte determines which of the upper pages of memory is selected for reading and writing. 0xh (Array x Selected) Where x = 1, 2, 3, 4 or 5 80h-F7h Customer EEPROM 87h DA % Adj Scale output of D/A converters by specified percentage Memory Location (Array 1) 00h-FFh Data EEPROM Memory Location (Array 2) 00h-Ffh Data EEPROM Memory Location (Array 3) 80h-81h Temperature High The value written to this location serves as Alarm the high alarm limit. Data format is the 88h-89h V_(cc) High Alarm same as the corresponding value 90h-91h B_(in) High Alarm (temperature, V_(cc), B_(in), P_(in), R_(in)). 98h-99h P_(in) High Alarm A0h-A1h R_(in) High Alarm 82h-83h Temperature Low The value written to this location serves as Alarm the low alarm limit. Data format is the 8Ah-8Bh V_(cc) Low Alarm same as the corresponding value 92h-93h B_(in) Low Alarm (temperature, V_(cc), B_(in), P_(in), R_(in)). 9Ah-9Bh P_(in) Low Alarm A2h-A3h R_(in) Low Alarm 84h-85h Temp High Warning The value written to this location serves as 8Ch-8Dh V_(cc) High Warning the high warning limit. Data format is the 94h-95h B_(in) High Warning same as the corresponding value 9Ch-9Dh P_(in) High Warning (temperature, V_(cc), B_(in), P_(in), R_(in)). A4h-A5h R_(in) High Warning 86h-87h Temperature Low The value written to this location serves as Warning the low warning limit. Data format is the 8Eh-8Fh V_(cc) Low Warning same as the corresponding value 96h-97h B_(in) Low Warning (temperature, V_(cc), B_(in), P_(in), R_(in)). 9Eh-9Fh P_(in) Low Warning A6h-A7h R_(in) Low Warning A8h-AFh, D_(out) control 0-8 Individual bit locations are defined in Table C5h 4. B0h-B7h, C6h F_(out) control 0-8 B8h-BFh, C7h L_(out) control 0-8 C0h Reserved Reserved C1h Prescale Selects MCLK divisor for X-delay CLKS. C2h D_(out) Delay Selects number of prescale clocks C3h F_(out) Delay C4h L_(out) Delay C8h-C9h V_(cc) —A/D Scale 16 bits of gain adjustment for corresponding CAh-CBh B_(in) —A/D Scale A/D conversion values. CCh-CDh P_(in) —A/D Scale CEh-CFh R_(in) —A/D Scale D0h Chip Address Selects chip address when external pin ASEL is low. D1h Margin #2 Finisar Selective Percentage (FSP) for D/A #2 D2h Margin #1 Finisar Selective Percentage (FSP) for D/A #1 D3h-D6h PW1 Byte 3 (D3h) The four bytes are used for password 1 MSB entry. The entered password will determine PW1 Byte 2 (D4h) the Finisar customer's read/write privileges. PW1 Byte 1 (D5h) PW1 Byte 0 (D6h) LSB D7h D/A Control This byte determines if the D/A outputs source or sink current, and it allows for the outputs to be scaled. D8h-DFh B_(in) Fast Trip These bytes define the fast trip comparison over temperature. E0h-E3h P_(in) Fast Trip These bytes define the fast trip comparison over temperature. E4h-E7h R_(in) Fast Trip These bytes define the fast trip comparison over temperature. E8h Configuration Override Location of the bits is defined in Table 4 Byte E9h Reserved Reserved EAh-EBh Internal State Bytes Location of the bits is defined in Table 4 ECh I/O States 1 Location of the bits is defined in Table 4 EDh-EEh D/A Out Magnitude of the temperature compensated D/A outputs EFh Temperature Index Address pointer to the look-up Arrays F0h-FFh Reserved Reserved Memory Location (Array 4) 00h-Ffh D/A Current vs. Temp #1 (User-Defined Look-up Array #1) Memory Location (Array 5) 00h-Ffh D/A Current vs. Temp #2 (User-Defined Look-up Array #2)

TABLE 2 DETAIL MEMORY DESCRIPTIONS - A/D VALUES AND STATUS BITS Byte Bit Name Description Converted analog values. Calibrated 16 bit data. (See Notes 1-2)  96 All Temperature MSB Signed 2's complement integer temperature (−40 to (60h) +125 C.) Based on internal temperature measurement  97 All Temperature LSB Fractional part of temperature (count/256)  98 All V_(cc) MSB Internally measured supply voltage in transceiver. Actual voltage is full 16 bit value * 100 uVolt.  99 All V_(cc) LSB (Yields range of 0-6.55 V) 100 All TX Bias MSB Measured TX Bias Current in mA Bias current is full 16 bit value * (1/256) mA. 101 All TX Bias LSB (Full range of 0-256 mA possible with 4 uA resolution) 102 All TX Power MSB Measured TX output power in mW. Output is full 16 bit value * (1/2048) mW. (see note 5) 103 All TX Power LSB (Full range of 0-32 mW possible with 0.5 μW resolution, or −33 to +15 dBm) 104 All RX Power MSB Measured RX input power in mW RX power is full 16 bit value * (1/16384) mW. (see note 6) 105 All RX Power LSB (Full range of 0-4 mW possible with 0.06 μW resolution, or −42 to +6 dBm) 106 All Reserved MSB Reserved for 1^(st) future definition of digitized analog input 107 All Reserved LSB Reserved for 1^(st) future definition of digitized analog input 108 All Reserved MSB Reserved for 2^(nd) future definition of digitized analog input 109 All Reserved LSB Reserved for 2^(nd) future definition of digitized analog input 110 7 TX Disable Digital state of the TX Disable Input Pin 110 6 Reserved 110 5 Reserved 110 4 Rate Select Digital state of the SFP Rate Select Input Pin 110 3 Reserved 110 2 TX Fault Digital state of the TX Fault Output Pin 110 1 LOS Digital state of the LOS Output Pin 110 0 Power-On-Logic Indicates transceiver has achieved power up and data valid 111 7 Temp A/D Valid Indicates A/D value in Bytes 96/97 is valid 111 6 V_(cc) A/D Valid Indicates A/D value in Bytes 98/99 is valid 111 5 TX Bias A/D Valid Indicates A/D value in Bytes 100/101 is valid 111 4 TX Power A/D Valid Indicates A/D value in Bytes 102/103 is valid 111 3 RX Power A/D Valid Indicates A/D value in Bytes 104/105 is valid 111 2 Reserved Indicates A/D value in Bytes 106/107 is valid 111 1 Reserved Indicates A/D value in Bytes 108/109 is valid 111 0 Reserved Reserved

TABLE 3 DETAIL MEMORY DESCRIPTIONS - ALARM AND WARNING FLAG BITS Byte Bit Name Description Alarm and Warning Flag Bits 112 7 Temp High Alarm Set when internal temperature exceeds high alarm level. 112 6 Temp Low Alarm Set when internal temperature is below low alarm level. 112 5 V_(cc) High Alarm Set when internal supply voltage exceeds high alarm level. 112 4 V_(cc) Low Alarm Set when internal supply voltage is below low alarm level. 112 3 TX Bias High Alarm Set when TX Bias current exceeds high alarm level. 112 2 TX Bias Low Alarm Set when TX Bias current is below low alarm level. 112 1 TX Power High Alarm Set when TX output power exceeds high alarm level. 112 0 TX Power Low Alarm Set when TX output power is below low alarm level. 113 7 RX Power High Alarm Set when Received Power exceeds high alarm level. 113 6 RX Power Low Alarm Set when Received Power is below low alarm level. 113 5-0 Reserved Alarm 114 All Reserved 115 All Reserved 116 7 Temp High Warning Set when internal temperature exceeds high warning level. 116 6 Temp Low Warning Set when internal temperature is below low warning level. 116 5 V_(cc) High Warning Set when internal supply voltage exceeds high warning level. 116 4 V_(cc) Low Warning Set when internal supply voltage is below low warning level. 116 3 TX Bias High Warning Set when TX Bias current exceeds high warning level. 116 2 TX Bias Low Warning Set when TX Bias current is below low warning level. 116 1 TX Power High Set when TX output power exceeds high Warning warning level. 116 0 TX Power Low Set when TX output power is below low Warning warning level. 117 7 RX Power High Set when Received Power exceeds high Warning warning level. 117 6 RX Power Low Set when Received Power is below low Warning warning level. 117 5 Reserved Warning 117 4 Reserved Warning 117 3 Reserved Warning 117 2 Reserved Warning 117 1 Reserved Warning 117 0 Reserved Warning 118 All Reserved 119 All Reserved

TABLE 4 DETAIL MEMORY DESCRIPTIONS - OTHER CONFIGURATION FLAGS Byte Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X-out cntl0 T alrm hi T alrm lo V alrm hi V alrm lo B alrm hi B alrm lo P alrm hi P alrm lo set set set set set set set set X-out cntl1 R alrm hi R alrm lo B ft hi set P ft hi set R ft hi set D-in inv D-in set F-in inv set set set set X-out cntl2 F-in set L-in inv L-in set Aux inv Aux set T alrm hi T alrm lo V alrm hi set set hib hib hib X-out cntl3 V alrm lo B alrm hi B alrm lo P alrm hi P alrm lo R alrm hi R alrm lo B ft hi hib hib hib hib hib hib hib hib X-out cntl4 P ft hi hib R ft hi hib D-in inv D-in hib F-in inv F-in hib L-in inv L-in hib hib hib hib X-out cntl5 Aux inv Aux hib T alrm hi T alrm lo V alrm hi V alrm lo B alrm hi B alrm lo hib clr clr clr clr clr clr X-out cntl6 P alrm hi P alrm lo R alrm hi R alrm lo B ft hi clr P ft hi clr R ft hi clr D-in inv clr clr clr clr clr X-out cntl7 D-in clr F-in inv F-in clr L-in inv L-in clr Aux inv Aux clr EE clr clr clr X-out cntl8 latch invert o-ride data o-ride S reset HI enable LO enable Pullup select select data enable Prescale reserved reserved Reserved reserved B³ B² B¹ B⁰ X-out delay B⁷ B⁶ B⁵ B⁴ B³ B² B¹ B⁰ chip address b⁷ b⁶ b⁵ b⁴ b³ b² b¹ X X-ad scale 2¹⁵ 2¹⁴ 2¹³ 2¹² 2¹¹ 2¹⁰ 2⁹ 2⁸ MSB X-ad scale 2⁷ 2⁶ 2⁵ 2⁴ 2³ 2² 2¹ 2⁰ LSB D/A cntl source/ D/A #2 range source/ D/A #1 range sink sink 1/0 2² 2¹ 2⁰ 1/0 2² 2¹ 2⁰ config/O- manual manual manual EE Bar SW-POR A/D Manual reserved ride D/A index AD alarm Enable fast alarm Internal D-set D-inhibit D-delay D-clear F-set F-inhibit F-delay F-clear State 1 Internal L-set L-inhibit L-delay L-clear reserved reserved reserved reserved State 0 I/O States 1 reserved F-in L-in reserved D-out reserved reserved reserved Margin #1 Reserved Neg_Scale2 Neg_Scale1 Neg_Scale0 Reserved Pos_Scale2 Pos_Scale1 Pos_Scale0 Margin #2 Reserved Neg_Scale2 Neg_Scale1 Neg_Scale0 Reserved Pos_Scale2 Pos_Scale1 Pos_Scale0 

1. A serial communications bus, comprising: a first module coupled to a second module via a serial cable, wherein each of the first and second modules comprise: a power interface configured to receive operating power for the respective module from an external power source; a controller configured to obtain digital diagnostic data representative of operational characteristics of at least the respective module; memory configured to store the digital diagnostic data; a first interface configured to allow an external host to read the digital diagnostic data from the memory; and a second interface distinct and separate from the first interface, the second interface configured to serially communicate data between the first module and the second module via the serial cable.
 2. The serial communications bus of claim 1, wherein the serial communication bus supports one or more of: a Serial Advanced Technology Attachment (SATA) standard; and a Serial Attached Small Computer System Interface (SAS) standard.
 3. The serial communications bus of claim 1, wherein the serial cable includes one of: an optical cable; and an electrically-conductive cable.
 4. The serial communications bus of claim 1, wherein the first interface is also configured to communicate with a host using one or more of: a Serial Advanced Technology Attachment (SATA) protocol; and a Serial Attached Small Computer System Interface (SAS) protocol.
 5. The serial communications bus of claim 1, wherein the first interface is also configured to allow an external host to write the digital diagnostic data to the memory.
 6. The serial communications bus of claim 1, wherein an external host can read the digital diagnostic data from and/or write the digital diagnostic data to the memory.
 7. The serial communications bus of claim 1, wherein the digital diagnostic data is stored in memory-mapped locations in the memory.
 8. The serial communications bus of claim 1, wherein each of the first and second modules comprise a voltage controller configured to encode digital diagnostic data onto a serial data signal by adjusting voltage levels of the serial data signal sent to a host.
 9. The serial communications bus of claim 1, wherein each of the first and second modules comprise a voltage amplitude sensor configured to decode digital diagnostic data encoded onto a serial data signal by determining voltage levels of the serial data signal sent from a host.
 10. The serial communications bus of claim 1, wherein the second interface includes a transmitter configured to transmit serial data signals through the serial cable.
 11. The serial communications bus of claim 10, wherein the serial cable is an electrically-conductive cable; and wherein the transmitter is configured to transmit electrical signals through the serial cable.
 12. The serial communications bus of claim 10, wherein the serial cable is an optical cable; wherein the transmitter is configured to: convert electrical signals into corresponding optical signals; and transmit optical signals through the serial cable; wherein the transmitter is a laser transmitter.
 13. The serial communications bus of claim 12, wherein the second interface circuit also includes a laser driver coupled to the laser transmitter, wherein the laser driver is configured to drive the laser transmitter.
 14. The serial communications bus of claim 1, wherein the second interface circuit includes a receiver configured to receive serial data signals from the serial cable.
 15. The serial communications bus of claim 14, wherein the serial cable is an electrically-conductive cable; and wherein the receiver is configured to receive electrical signals from the serial cable.
 16. The serial communications bus of claim 14, wherein the serial cable is an optical cable; wherein the receiver is configured to: receive optical signals from the serial cable; and convert the optical signals into corresponding electrical signals; and wherein the receiver is a photodiode.
 17. The serial communications bus of claim 16, wherein the second interface circuit also includes a post-amplifier coupled to the photodiode, wherein the post-amplifier is configured to generate a fixed output signal.
 18. The serial communications bus of claim 1, wherein the digital diagnostic data includes one or more of: a transfer speed for the serial cable; voltage amplitudes of signals received from the serial cable and or the host; an optical power level of an optical signal received from the serial cable; and a number of faults.
 19. The serial communications bus of claim 1, wherein each of the first and second modules is coupled to a host.
 20. A serial communications bus, comprising: serial communications module, comprising: a power interface configured to receive operating power for the module from an external power source; a controller configured to obtain digital diagnostic data representative of operational characteristics of the module; memory configured to store the digital diagnostic data; a first interface configured to allow an external host to read the digital diagnostic data from the memory; and a second interface configured to serially communicate data to a second module via a serial cable coupled to the second interface circuit.
 21. The serial communications bus of claim 20, wherein the serial communication bus supports one or more of: a Serial Advanced Technology Attachment (SATA) standard; and a Serial Attached Small Computer System Interface (SAS) standard.
 22. The serial communications bus of claim 20, wherein the serial cable includes one of: an optical cable; and an electrical cable.
 23. The serial communications bus of claim 20, wherein the first interface is also configured to communicate with a host using one or more of: a Serial Advanced Technology Attachment (SATA) protocol; and a Serial Attached Small Computer System Interface (SAS) protocol.
 24. The serial communications bus of claim 20, wherein the first interface is also configured to allow an external host to write the digital diagnostic data to the memory.
 25. The serial communications bus of claim 20, wherein the digital diagnostic data is stored in memory-mapped locations in the memory.
 26. A method, comprising: at a powered module for a serial cable, receiving a request for digital diagnostic data for the powered module from a requester; locating the digital diagnostic data from the powered module; encoding the digital diagnostic data onto a serial data signal while preserving the original data in the serial data signal; and transmitting the serial data signal to the requester.
 27. The method of claim 26, wherein prior to receiving a request for the digital diagnostic data, the method further comprises: monitoring at least the powered module to obtain digital diagnostic data; and storing the obtained digital diagnostic data into a memory of the powered module.
 28. The method of claim 27, wherein the monitoring is performed by one or more of: the powered module; and an external device.
 29. The method of claim 26, further comprising: receiving at the powered module the serial data signal from an additional host via the serial cable; and transmitting the serial data signal to the host.
 30. The method of claim 26, wherein encoding the digital diagnostic data onto the serial data signal while preserving the original data in the serial data signal includes: serializing the digital diagnostic data; determining a series of voltage levels for the serialized digital diagnostic data based on a voltage encoding map; and adjusting voltage levels for the serial data signal based on the determined series of voltage levels.
 31. The method of claim 29, wherein the digital diagnostic data can be encoded into one or more voltage levels in the serial data signal.
 32. The method of claim 26, wherein the digital diagnostic data includes one or more of: a transfer speed for the serial cable; voltage amplitudes of signals received from the serial cable and or the host; an optical power level of an optical signal received from the serial cable; and a number of faults.
 33. The method of claim 26 wherein the requester includes one or more of: a host system; and another powered module.
 34. A method, comprising: receiving a serial data signal which includes encoded digital diagnostic data from a sender; obtaining the digital diagnostic data from the serial data signal; and storing the digital diagnostic data in memory.
 35. The method of claim 34, wherein obtaining the digital diagnostic data from the serial data signal includes: determining a series of voltage levels for the serial data signal; obtaining serialized digital diagnostic data from the determined series of voltage levels based on a voltage encoding map; and deserializing the serialized digital diagnostic data to obtain the digital diagnostic data.
 36. The method of claim 35, wherein the digital diagnostic data can be encoded into one or more voltage levels in the digital diagnostic signal.
 37. The method of claim 34, wherein the digital diagnostic data includes one or more of: a transfer speed for the serial cable; voltage amplitudes of signals received from the serial cable and or the host; an optical power level of an optical signal received from the serial cable; and a number of faults.
 38. The method of claim 34, wherein the sender includes one of: a powered module; and a host system.
 39. The method of claim 34, wherein the memory is one of: a memory for the powered module; and a memory for a host system. 